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3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
Features
256K x 16 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle times - Commercial and Industrial: 10/12/15ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Single 3.3V power supply Available in 44-pin, 400 mil plastic SOJ package and a 44pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package.
IDT71V416S IDT71V416L
Description
The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized as 256K x 16. It is fabricated using IDT's high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71V416 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a 44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package.
x x x
x x
x x x x
Functional Block Diagram
OE Output Enable Buffer
A0 - A17
Address Buffers
Row / Column Decoders
8 CS Chip Select Buffer 8 Sense Amps and Write Drivers
High Byte Output Buffer High Byte Write Buffer
8 I/O 15
8 I/O 8
4,194,304-bit Memory Array
WE Write Enable Buffer
16
8
Low Byte Output Buffer Low Byte Write Buffer
8 I/O 7
8
8
I/O 0
BHE Byte Enable Buffers BLE 3624 drw 01
JULY 2003
1
(c)2003 Integrated Device Technology, Inc. DSC-3624/07
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations - SOJ/TSOP
A0 A1 A2 A3 A4 CS I/O 0 I/O 1 I/O 2 I/O 3 VDD VSS I/O 4 I/O 5 I/O 6 I/O 7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O 15 I/O 14 I/O 13 I/O 12 VSS VDD I/O 11 I/O 10 I/O 9 I/O 8 NC* A14 A13 A12 A11 A10
Pin Configurations - 48 BGA
1 A B C D E F G H BLE I/O0 I/O1 VSS VDD I/O6 I/O7 NC 2 OE BHE I/O2 I/O3 I/O4 I/O5 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CS I/O10 I/O11 I/O12 I/O13 WE A11 6 NC I/O8 I/O9 VDD VSS I/O14 I/O15 NC
3624 tbl 11
SO44-1 SO44-2
3624 drw 02
*Pin 28 can either be a NC or connected to Vss
Top View Pin Descriptions
A0 - A17 CS WE OE BHE BLE I/O0 - I/O15 VDD VSS Address Inputs Chip Select Write Enable Output Enable High Byte Enable Low Byte Enable Data Input/Output 3.3V Power Ground Input Input Input Input Input Input I/O Pwr Gnd
3624 tbl 01
SOJ Capacitance
(TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 7 8 Unit pF pF
3624 tbl 02
48 BGA Capacitance
(TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 6 7 Unit pF pF
3624 tbl 02b
NOTE: 1. This parameter is guaranteed by device characterization, but not production tested.
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IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VDD VIN, VOUT TBIAS TSTG PT IOUT Rating Supply Voltage Relative to VSS Terminal Voltage Relative to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +4.6 -0.5 to VDD+0.5 -55 to +125 -55 to +125 1 50 Unit V V
o o
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0OC to +70OC -40 C to +85 C
O O
VSS 0V 0V
VDD See Below See Below
3624 tbl 05
C C
W mA
3624 tbl 04
Recommended DC Operating Conditions
Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3(2) Typ. 3.3 0
____
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Max. 3.6 0 VDD+0.3 0.8
(1)
Unit V V V V
3624 tbl 06
____
NOTES: 1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = -2V for pulse width less than 5ns, once per cycle.
Truth Table(1)
CS H L L L L L L L L OE X L L L X X X H X WE X H H H L L L H X BLE X L H L L L H X H BHE X H L L L H L X H I/O0-I/O7 High-Z DATAOUT High-Z DATAOUT DATAIN DATAIN High-Z High-Z High-Z I/O8-I/O15 High-Z High-Z DATAOUT DATAOUT DATAIN High-Z DATAIN High-Z High-Z Function Deselected - Standby Low Byte Read High Byte Read Word Read Word Write Low Byte Write High Byte Write Outputs Disabled Outputs Disabled
3624 tbl 03
NOTE: 1. H = VIH, L = VIL, X = Don't care.
6.42 3
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V416 Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = Max., VIN = VSS to VDD VDD = Max., CS = VIH, VOUT = VSS to VDD IOL = 8mA, VDD = Min. IOH = -4mA, VDD = Min. Min.
___ ___ ___
Max. 5 5 0.4
___
Unit A A V V
3624 tbl 07
2.4
DC Electrical Characteristics(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD - 0.2V)
71V416S/L10 Symbol ICC Parameter Dynamic Operating Current CS < VLC, Outputs Open, VDD = Max., f = fMAX(4) Dynamic Standby Power Supply Current CS > VHC, Outputs Open, VDD = Max., f = fMAX(4) Full Standby Pow er Supply Current (static) CS > VHC, Outputs Open, VDD = Max., f = 0(4) S L S L S L Com'l. 200 180 70 50 20 10 Ind.(5) 200 -- 70 -- 20 -- 71V416S/L12 Com'l. 180 170 60 45 20 10 Ind. 180 170 60 45 20 10 71V416S/L15 Com'l. 170 160 50 40 20 10 Ind. 170 160 50 40 20 10
3624 tbl 08
Unit mA
ISB
mA
ISB1
mA
NOTES: IDT71V416S/71V416L 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD -0.2V (High). 3. Power specifications are preliminary. 4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 5. Standard power 10ns (S10) speed grade only.
AC Test Loads
+1.5V 50 I/O Z0 = 50 30pF
3624 drw 03
3.3V 320 DATA OUT 5pF* 350
3624 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7 6 tAA, tACS (Typical, ns) 5 4 3
* * *
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 1.5ns 1.5V 1.5V Figures 1,2 and 3
3624 tbl 09
2 1
* * *
*
8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF)
3624 drw 05
Figure 3. Output Capacitive Derating
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IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V416S/L10(2) Symbol READ CYCLE tRC tAA tACS tCLZ
(1) (1)
71V416S/L12 Min. Max.
71V416S/L15 Min. Max. Unit
Parameter
Min.
Max.
Read Cycle Time Address Access Time Chip Select Access Time Chip Select Low to Output in Low-Z Chip Select High to Output in High-Z Output Enable Low to Output Valid
(1) (1)
10
____
____
12
____
____
15
____
____
ns ns ns ns ns ns ns ns ns ns ns ns
10 10
____
12 12
____
15 15
____
____
____
____
4
____
4
____
4
____
tCHZ tOE tOLZ
5 5
____
6 6
____
7 7
____
____
____
____
Output Enable Low to Output in Low-Z Output Enable High to Output in High-Z Output Hold from Address Change Byte Enable Low to Output Valid
0
____
0
____
0
____
tOHZ tOH tBE tBLZ
5
____
6
____
7
____
4
____
4
____
4
____
5
____
6
____
7
____
(1) (1)
Byte Enable Low to Output in Low-Z Byte Enable High to Output in High-Z
0
____
0
____
0
____
tBHZ
5
6
7
WRITE CYCLE tWC tAW tCW tBW tAS tWR tWP tDW tDH tOW(1) tWHZ
(1)
Write Cycle Time Address Valid to End of Write Chip Select Low to End of Write Byte Enable Low to End of Write Address Set-up Time Address Hold from End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Enable High to Output in Low-Z Write Enable Low to Output in High-Z
10 8 8 8 0 0 8 5 0 3
____
____
12 8 8 8 0 0 8 6 0 3
____
____
15 10 10 10 0 0 10 7 0 3
____
____
ns ns ns ns ns ns ns ns ns ns ns
3624 tbl 10
____
____
____
____
____
____
____
____
____
____ ____
____ ____
____ ____
____
____
____
____
____
____
____
____
____
____
____
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6
7
7
NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 2. Low power 10ns (L10) speed 0C to +70C temperature range only.
Timing Waveform of Read Cycle No. 1(1,2,3)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID
D A T AOUT V AL ID
tOH
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW.
36 2 4 drw 06
6.42 5
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
(1)
Timing Waveform of Read Cycle No. 2
tRC ADDRESS tAA OE tOE CS tCLZ BHE, BLE tBE tBLZ DATAOUT
(3) (2) (3)
tOH
tOHZ (3)
tOLZ tACS (2)
(3)
tCHZ (3)
tBHZ (3) DATA OUT VALID
3624 drw 07
NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured 200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC ADDRESS tAW CS tCW BHE, BLE tWR WE tAS tWHZ DATAOUT PREVIOUS DATA VALID
(3) (5)
(2)
tCHZ
(5)
tBW
(5)
tBHZ
tWP
tOW tDH
(5)
DATA VALID tDW
DATAIN
DATAIN VALID
3624 drw 0
NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state.
6.42 6
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3)
tWC ADDRESS tAW CS tAS tBW BHE, BLE tWP WE tWR tCW (2)
DATAOUT tDW DATAIN DATAIN VALID
3624 drw 09
tDH
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,3)
tWC ADDRESS tAW CS tCW tAS BHE, BLE tWP WE tWR
(2)
tBW
DATAOUT tDW DATAIN tDH
DATAIN VALID
3624 drw 10
NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. During this period, I/O pins are in the output state, and input signals must not be applied. 3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6.42 7
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71V416 Device Type X X Power XX Speed XXX Package X Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C)
Y PH BE
44-pin, 400-mil SOJ (SO44-1) 44-pin TSOP Type II (SO44-2) 48 Ball Grid Array
10* 12 15
Speed in nanoseconds
S L Blank Y
Standard Power Low Power First Generation or current stepping being shipped Second Generation die step
* Commercial only for low power 10ns (L10) speed grade.
3624 drw 11a
6.42 8
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
08/5/99 08/31/99 03/24/00 08/10/00 09/11/ 02 11/26/02 07/31/03 Pg 6 Pg. 1-9 Pg. 9 Pg. 6 Pg. 1 Pg. 2 Pg. 8 Pg. 8 Updated to new format Revised footnote for tCW on Write Cycle No. 1 diagram Added Industrial temperature range offering Added Datasheet Document History Changed note to Write cycle No. 1 according to footnotes Add 48 ball grid array package offering Correct TTL to LVTTL Updated TBD information for the 48 BGA Capacitance table Added "Die Revision" to ordering information Updated note, L10 speed grade commercial temperature only and updated die stepping from YF to Y.
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
6.42 9
for Tech Support: sramhelp@idt.com 800-544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.

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